Computational Locking employs ideas of runtime gradient descent to "solve" for PLL lock, dramatically improving lock-time
Multi-core server processors, heterogeneous mobile SoCs, and an increasing number of IoT applications can experience significant power and performance benefits from PLL lock-time reduction during wakeup (cold-start) and re-lock. Existing PLLs feature lock-times of approximately 100 REFCLK cycles: for relock. Fast lock-techniques have been proposed but they assume no temperature variation, require prior knowledge of PVT gain or incur significant steady-state performance degradation. In this project, we proposed, and successfully demonstrated a technique that performs runtime computation of accurate phase-frequency PLL equations to robustly achieve phase-lock 8x more rapidly than traditional all-Digital PLL (ADPLL) architectures. To further support Computational Lock, we also developed a novel wide dynamic-range, high resolution and fast resolving TDC architecture. Computational Lock does not impact steady-state PLL operation and can be applied to a broad range of ADPLLs. We demonstrate the proposed technique on a 1-2 GHz ADPLL intended for system clocking applications in 65nm CMOS.
More details can be found in our VLSI Symposium Paper