UniCaP (Switched-Capacitor) for sub-Vth systems¶
The proliferation of Internet-of-Things (IoT) devices has provided an unprecedented demand for ultra-low power systems, where dissipative Process, Voltage and Temperature (PVT) related supply margins, and low cost, low form-factor power management solutions are key considerations. Switched Capacitor (SC) converters are well-suited to such systems and offer efficient integrated DC-DC conversion. However, poor load regulation results in additional droop guard-bands, amplifying the existing problem of PVT-margin related inefficiencies. Another challenge facing low-voltage (near- and sub-threshold) systems is the need to achieve fine-grained voltage scalability with good load regulation. Several integrated voltage regulation (IVR) solutions have been proposed to address supply and PVT-related margins.
This project sees to develop an all-digital Unified Clock and Power (UniCaP) architecture for performance-regulation of near-Vth and sub-Vth digital systems, and demonstrate its effectiveness on an ARM Cortex-M0 processor with an FFT accelerator. UniCaP is based on the observation supply-voltage control in low-voltage digital systems is tasked with ensuring timing-slack. The central idea behind this UniCaP design is to use canary-based oscillators powered by the noisy load domain (Vdd) to guarantee timing compliance, and incorporate voltage-regulation into a Frequency Locked Loop to control Vdd to regulate system operating frequency (fclk) under PVT variation and supply noise. Key features demonstrated by test measurements include (i) a 92% average reduction in supply-droop margin (ii) 98% reduction of temperature related Vdd margins amounting to XmV (YmV) at 0.45V (0.56V) Vdd in the -20C—100C range (iii) continuous SC Vdd-scalability with excellent load and line regulation (iv) a floating split-level supply rail for robust, efficient SC operation independent of Vdd conversion and (v) simplified, on-the-fly DVFS avoiding use of Voltage-frequency tables and enabling uninterrupted processor operation.
More details will be posted upon publication of this work.